1 AnswerCalculate the size of each address in m bits. If main memory has 2048 bytes, then we have 2048=2^m unique addresses. ... Calculate bit offset n from the number of bytes in a block. 64 bytes/8 blocks = 8 bytes per block. ... Calculate the set index s. ... Finally, we know the number of tag bits is T=m-s-n.
The incoming address to the cache is divided into bits for offset and tag. Tag corresponds to the remaining bits. This means there are 14 – (2) = 12 tag bits, which are stored in tag field to match the address on cache request.
Example: 4-way set associative cache: Cache line = 32 bytes (256 bits). Number of Sets = Number of cache lines / Associativity = 16/4 = 4. Set address width = Log2(Number of sets) = Log2(4) = 2. TAG width = Full address width - SET width - Offset width = 16 - 2 -5 = 9 Bits.
The L2 cache is 256 Kbytes divided over 16-way sets, making 16 Kbytes addressable, which leads once again to a 14 – 6 = 8 bit index and 18 bit tag.
Each set contains two ways or degrees of associativity. Each way consists of a data block and the valid and tag bits. The cache reads blocks from both ways in the selected set and checks the tags and valid bits for a hit. If a hit occurs in one of the ways, a multiplexer selects data from that way.
The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache.
2:3412:52And in order to do so we need to divide the number of cache lines by the set. Size which will giveMoreAnd in order to do so we need to divide the number of cache lines by the set. Size which will give us 2 to the power 12 therefore 12 bits will be used for the set number portion.
For a 4-way associative cache each set contains 4 cache lines. Each cache line consists of a "tag" and a "data" field. There is also a "valid" bit, which is not shown. The tag portion of the request address is compared to all of the tag fields in the selected set.
• Set associative caches are a. compromise between fully associative caches and direct-mapped caches. In a set associative cache, there are a fixed number of locations (called a set) that a given address may be stored in. The number of locations in each set is the associative of the cache.
L2 and L3 caches are bigger than L1. They are extra caches built between the CPU and the RAM. Sometimes L2 is built into the CPU with L1. L2 and L3 caches take slightly longer to access than L1. The more L2 and L3 memory available, the faster a computer can run.
L1 is "level-1" cache memory, usually built onto the microprocessor chip itself. For example, the Intel MMX microprocessor comes with 32 thousand bytes of L1. L2 (that is, level-2) cache memory is on a separate chip (possibly on an expansion card) that can be accessed more quickly than the larger "main" memory.
L1 is located on CPU chip, L2 is located between processor and main memory, but there is a point to know that in some system L2 is located on CPU chip while in some other system L2 is located on mother board itself, and L3 is constantly located on main board chip.